/*
Copyright (c) 2019 Alibaba Group Holding Limited

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/
#include "stdio.h"
#include "vtimer.h"
#include "datatype.h"

//*******************************
//             PMU
//*******************************
#define PMU_BASE 0x60030000

#define PMU_EN_REG  0X00
#define PMU_PC_REG  0X04

#define IOPMP_BASE 0x40200000
#define IOPMP_RULE_REG  0X00
#define IOPMP_ERROR_REG  0X04

#define DMA_BY_DEP  0xfff
#define DMA_REE_INC_START_PC 0xf0000000 //ree的程序在tee的iram中的地址
#define DMA_BY_DEST_BASE     0x20025000 //定义dest地址
#define DMA_BY_SRC_BASE      0x00008000//定义src地址
#define DMA_BLK_NUM          0X01      //DMA搬移block的数量

//*******************************
//          USI0 UART
//*******************************
#define USI0_BADDR  0x50028000
#define USI2_BADDR  0x50029000

#define USI1_BADDR  0x60028000
#define REG32(addr) *((volatile unsigned int *)(addr))

#define USI_CTRL    0x00
#define MODE_SEL    0x04
#define TX_FIFO     0x08
#define RX_FIFO     0x08
#define FIFO_STA    0x0c
#define CLK_DIV0    0x10
#define UART_CTRL   0x18
#define UART_STA    0x1c
//*******************************
//          TIMER
//*******************************

#define TIM0_BASE 0x50000000
#define TIM2_BASE 0x50000400

#define TIMER1_LD_CNT   0X00
#define TIMER1_CUR_VLU  0X04
#define TIMER1_CTRL_REG 0X08
#define TIMER1_INT_CLR  0X0C
#define TIMER1_INT_STA  0X10

#define TIMER2_LD_CNT   0X14
#define TIMER2_CUR_VLU  0X18
#define TIMER2_CTRL_REG 0X1C
#define TIMER2_INT_CLR  0X20
#define TIMER2_INT_STA  0X24

//*******************************
//          MAILBOX
//*******************************
#define REE2TEE_BASE 0x40010000

#define REE2TEE_REG0 0X00
#define REE2TEE_REG1 0X04
#define REE2TEE_REG2 0X08
#define REE2TEE_REG3 0X0C
#define REE2TEE_ACCESS_ERROR 0X10

#define TEE2REE_BASE 0x40020000

#define TEE2REE_REG0 0X00
#define TEE2REE_REG1 0X04
#define TEE2REE_REG2 0X08
#define TEE2REE_REG3 0X0C
#define TEE2REE_ACCESS_ERROR 0X10

void tee_timer_delay (uint32_t cnt_num)
{
int int_tim_flag=0;
int int_tim_eoi=0;

//disable Timer1

    *(volatile uint32_t *) (TIM2_BASE+TIMER1_CTRL_REG)  = 0x2;
//Timer1 counter
    *(volatile uint32_t *) (TIM2_BASE+TIMER1_LD_CNT)    = cnt_num;//0x400
//enable Timer1
    *(volatile uint32_t *) (TIM2_BASE+TIMER1_CTRL_REG)  = 0x3;
    int_tim_flag= *(volatile uint32_t *) (TIM2_BASE+TIMER1_INT_STA);
//wait timer interrupt state
    while (  int_tim_flag != 0x1){
	    int_tim_flag= *(volatile uint32_t *) (TIM2_BASE+TIMER1_INT_STA);
	}

//clear timer interrut state
   int_tim_eoi = *(volatile uint32_t *) (TIM2_BASE+TIMER1_INT_CLR);
}

void ree_timer_delay (uint32_t cnt_num)
{
int int_tim_flag=0;
int int_tim_eoi=0;

//disable Timer1

    *(volatile uint32_t *) (TIM0_BASE+TIMER1_CTRL_REG)  = 0x2;
//Timer1 counter
    *(volatile uint32_t *) (TIM0_BASE+TIMER1_LD_CNT)    = cnt_num;//0x400
//enable Timer1
    *(volatile uint32_t *) (TIM0_BASE+TIMER1_CTRL_REG)  = 0x3;
    int_tim_flag= *(volatile uint32_t *) (TIM0_BASE+TIMER1_INT_STA);
//wait timer interrupt state
    while (  int_tim_flag != 0x1){
	    int_tim_flag= *(volatile uint32_t *) (TIM0_BASE+TIMER1_INT_STA);
	}

//clear timer interrut state
   int_tim_eoi = *(volatile uint32_t *) (TIM0_BASE+TIMER1_INT_CLR);
}

int tee_main (void)
{
    int int_dma_flag=0;
    int i =0;
    uint32_t data_check=0;
    uint32_t dma_index;
    uint32_t dma_jndex;
    printf("---------------------------------\n");
    printf("-------------TEE-----------------\n");
    printf("---------------------------------\n");
    printf("tee core process : running safety procedures\n");

    // data_check = *(volatile uint32_t *) (0x0000004c);
    // printf("tee core process : tee core data is %x\r\n",data_check);
    //设置REE的IOPMP访问权限，限制REE对TIMER0的访问
    printf("tee core process : SET IOPMP rule and limit access to TIMER0\r\n");
     //USI0 R W ,USI2 W
    *(volatile uint32_t *)(IOPMP_BASE+IOPMP_RULE_REG) = 0xFFFFFbFF;
    //检查设置的权限情况
    data_check = *(volatile uint32_t *) (0x40200000);
    printf("tee core process : IOPMP rule is %x\r\n",data_check);

    // //打印提示信息 ： 唤醒REE core
      printf("tee core process : tee core wakes up ree core\n");
    // //先向ree pc指针写入复位值
    *(volatile uint32_t *)(PMU_BASE+PMU_PC_REG) = 0x90000000;
    // //唤醒REE core
    *(volatile uint32_t *)(PMU_BASE+PMU_EN_REG) = 0x00000002;

     while(1)
	{

             tee_timer_delay(0x1000);
                 if(i == 10){
                        //USI0 R ,USI2 W
                    *(volatile uint32_t *)(IOPMP_BASE+IOPMP_RULE_REG) = 0xFFFFF9FF;
                            REG32(USI0_BADDR+CLK_DIV0) = 0x02;
                     printf("TEE SET USI \r\n");
                    }
                 else if (i == 20)
                          //USI0 W ,USI2 R W
                   *(volatile uint32_t *)(IOPMP_BASE+IOPMP_RULE_REG) = 0xFFFFFeFF;
                    else if(i == 30)
                           i=9;
                    i= i+1;
             // printf("TEE core process : illaccess 0x%x \r\n",REG32(IOPMP_BASE+IOPMP_ERROR_REG));
             // printf("TEE core process : USI 0x%x \r\n",REG32(USI0_BADDR+CLK_DIV0));
	}
            sim_end(); 

}

int ree_main (void)
{
    printf("\n");
    printf("---------------------------------\n");
    printf("-------------REE-----------------\n");
    printf("---------------------------------\n");

    while(1)
    {
          printf("REE core process : USI2 0x%x \r\n",REG32(USI2_BADDR+CLK_DIV0));
          printf("REE core process : USI0 0x%x \r\n",REG32(USI0_BADDR+CLK_DIV0));
          REG32(USI2_BADDR+CLK_DIV0) = 0x22;
          REG32(USI0_BADDR+CLK_DIV0) = 0x67;
          printf("REE core process : USI2 0x%x \r\n",REG32(USI2_BADDR+CLK_DIV0));
          printf("REE core process : USI0 0x%x \r\n",REG32(USI0_BADDR+CLK_DIV0));

          // ree_timer_delay (0x1000);
             // verify whether REE can mod IOPMP reg
        //*(volatile uint32_t *)(IOPMP_BASE+IOPMP_RULE_REG) = 0xFFFFFFFF; 
         ree_timer_delay (800);
         //sim_end(); 
             
    };

   
 

    
}



    // for (dma_jndex = 0;dma_jndex < 8; dma_jndex++)
    // {
    //     for (dma_index = 0;dma_index < DMA_BY_DEP/4+1; dma_index++)
    //     {
    //         data_check = *(volatile uint32_t *) (DMA_BY_SRC_BASE + dma_jndex * (DMA_BY_DEP + 0x1) + dma_index * 4);
    //         printf("%x\r\n",data_check);
    //     }
    //     printf("ree core process : this is %d block!\n",dma_jndex);
    // }


